Semiconductor
As a Digital Layout Engineer, you will:
Own the Physical Design workpackages: Floor-planning, Placement, CTS,
Routing, Sign-Off – including: planning, effort estimation and implementation.
Be responsible for the quality of the physical design and the fulfillment of the
required KPIs.
Work together with the physical design verification and synthesis owners to
reach the timing closure and signoff criteria as planned.
Interface with top level, digital and analog design teams both local and from
other sites to ensure a smooth integration at top.
Implement, update and improve the scripts used in our Physical Design flow
You are an innovative, creative and open-minded person with a great team spirit and
willingness to cooperate closely with international and cross-functional integrated
project teams. Furthermore, you enjoy connecting with other people and are flexible for
business trips and trainings.
You are fitting for this role if you have:
Proven experience in implementing complex SoC designs from RTL to GDS à
preferred in an UNIX environment.
Expertise in floor-planning, power, CTS, place and route and physical verification
with knowledge of synthesis and timing analysis.
Skills acquired by previous usage of various CAD tools like: ICC/ICC2, Calibre,
StarRC -> Primetime and Design Compiler is considered a plus.
Knowledge of bonding diagrams generation.
Very good scripting knowledge using TCL, Python and/or Perl.
Previous experience with physical design work-packages planning (including
effort estimation) and risk management.
Very good communication skills and fluency in English
